Digital signal processing has typically been effected only using the linear number system. However, a digital signal processor for general purpose calculating may be efficiently implemented in the logarithmic number system as taught in U.S. Pat. No. 4,682,302, assigned to the assignee hereof and entitled "A Logarithmic Arithmetic Logic Unit". When implementing digital signal processing algorithms, a maximum value of a plurality of operands must typically be chosen. In a linear number system, a maximum valued operand in a plurality of operands is typically found by determining the bit position of the most significant bit of each operand. This is an easy calculation which is readily made by electronic hardware. However, since others have not implemented digital signal processors in the logarithmic number system, the need to efficiently determine a maximum logarithmic valued operand in a plurality of logarithmic operands has not been adequately addressed. Due to the nonlinear nature of the logarithmic number system, a maximum valued operand cannot be determined by the method previously used for linear numbers.